Military

MathWorks debuts HDL code generation, verification for FPGA, ASIC, standards-compliant designs

NATICK, Mass., 6 March 2012. MathWorks has unveiled HDL Coder, its new product that automatically generates HDL code from MATLAB, and HDL Verifier, which offers FPGA hardware-in-the-loop capabilities ...
Electronic Design

The MathWorks App Generates HDL Code From System Models

The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It produces ...
EDN

Automating rule sets for safety-critical HDL coding

During the development process for safety-critical designs, all precautions should be taken to prevent device failures from all foreseeable sources, including those due to poor design methods and ...
Electronic Design

"Missing Link" Generates HDL Code From Simulink/Matlab Models

A persistent bugaboo in adopting electronic system-level (ESL) design methodologies is how to avoid wasting the work done above RTL. Certainly, designers of DSPs in particular have enjoyed using the ...
EDN

HDL makeover from creation to integration to validation

As system-on-chip (SoC) designs become more complex and powerful, catching potential errors and issues in specifications at the front-end of the design cycle is now far more critical. An EDA outfit ...
Military

Aldec offers finite state machine coverage for verification of safety-critical FPGAs

HENDERSON, Nev. Aldec Inc. is introducing the latest version of its mixed-language, field-programmable gate array (FPGA) design and simulation platform, Active-HDL 10.4, providing finite-state machine ...